This invention relates to a level detection circuit for detecting the signal level of input signals and, more particularly, to such a circuit employed in an automatic color saturation control (ACC).
A television receiver or the video tape recorded, for example, is provided with an automatic Color saturation control (ACC) circuit. In the television receiver, if the level difference between luminance signals and the carrier chrominance signals fluctuates because for example of fluctuations in the received electrical waves or mismatching of an antenna system, saturation on a display screen is changed in an irregular manner. Besides, solely the color saturation may be changed by channel switching. Consequently, the aforementioned ACC circuit is built into the television receiver for automatically adjusting the gain of the bandwidth amplifying circuit which is operated for maintaining a constant level of the carrier chrominance signals applied to a demodulation circuit. The ACC circuit, which compares a burst amplitude value to a reference value for controlling the gain for maintaining the color saturation at all times at a constant level, is arranged as shown for example in FIG. 1.
In this figure, carrier chrominance signals are supplied to an input terminal 21 of the ACC circuit and thence supplied to a level detection circuit 25 via a multiplier 23. The level detection circuit 25 detects the level of the carrier chrominance signals. Since the chroma level is determined by the level of a burst signal, the level detection circuit 25 detects the level of the carrier chrominance signal, that is the burst amplitude, when a burst gate pulse supplied via terminal 22 from a sync deflection block of the television receiver is at e.g. a high "H" level.
The ACC circuit decides a loop gain by integrating the difference between the level detection output from the level detection circuit 25 and a reference. That is, with the present ACC circuit, the level detection outpost of the level detection circuit 25 is supplied as an additive signal to an additive node 26 also supplied with a predetermined reference value as a subtractive signal from a level reference value generating circuit 28. A difference output between the level reference value and the level detection output is produced by the additive node 26 so as to be supplied to an integrating circuit 27. An integrated output of the integrating circuit 27 is supplied as a multiplication coefficient to the multiplier 23. The carrier chrominance signal from multiplier 22 is multiplied by the multiplication coefficient from the integrating circuit 27. A multiplication signal from multiplier 23 is outputted as ACC output at an output terminal 24 so as to be supplied to a downstream decoder, not shown.
The aforementioned burst gate pulse is generated in the following manner. For example, horizontal synchronization signal H.sub.SY is extracted from a composite video signal shown in FIG. 2, by a sync separator, not shown, provided within the deflection system. The horizontal synchronization signal H.sub.SY is differentiated, as shown in FIG. 3, and a rising part of the differentiated waveform is cut along a threshold value V.sub.TH for producing the aforementioned burst gate pulse which is a pulse having a position corresponding to the burst, period.
Meanwhile, in the above-mentioned level detection circuit 25, shown in FIG. 1, a square root value is found for finding the burst amplitude of the color chrominance signals. Typical of the prior-art arrangements for finding the square root is an arrangement employing a read-only memory (ROM).
However, if higher precision in square root calculation is desired in the arrangement for finding the square root by ROM, the number of address bits of ROM and the number of bits of data stored in ROM are increased so that a ROM of larger capacity is required and hence the circuit is undesirably increased in size.